The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
A digital to analog converter (DAC) converts digital data into an analog signal. When operating at high speeds, the digital data received by the DAC typically needs to meet various timing requirements. For example only, the system needs to account for timing variations in the DAC that occur due to variations in process, supply voltage and temperature (PVT). The system also needs to account for timing variations that occur in a circuit such as a field programmable gate array (FPGA) or application specific integrated circuit (ASIC) that generates the digital data. Meeting the timing requirements ensures that a data latch clock of the DAC can reliably latch the digital data and achieve a desired dynamic performance.
A data interface between the FPGA or ASIC and the DAC becomes more difficult to implement as the speed of the DAC increases. For example only, one DAC implementation operates at 4 Giga samples per second (Gsps). A 4-to-1 multiplexer may be used at an input of the DAC, which reduces a digital data rate to 1 Gbps. In this application, there is only a 1 nanosecond (ns) time slot for the data interface for each bit of the digital data in a 16 bit digital data bus.
Several conventional implementations of the data interface will be described below in conjunction with FIGS. 1-5. Referring now to FIGS. 1 and 2, a system 20 includes a circuit 24 such as a FPGA, ASIC or other circuit that generates digital data. The circuit 24 may include a serializer circuit 30 that outputs digital data to a DAC 28 via a buffer 34. The DAC 28 includes a multiplexer 42 that receives the digital data and a clock data signal (CLK_data). The multiplexer 42 may be a 4:1 multiplexer. An output of the multiplexer 42 is transmitted to a DAC core 44. The DAC 28 further includes a clock divider circuit 48 that receives a DAC clock (CLK_dac) signal. The clock divider circuit 48 may divide the CLK_dac signal by a divisor. An output of the clock divider circuit 48 supplies the CLK_data signal to an input of the multiplexer 42 and a buffer 52. The buffer 52 outputs a data clock (DATACLK) signal to a buffer 56 of the circuit 24. The buffer 56 transmits the DATACLK signal to the serializer circuit 30.
The DATACLK signal after the buffer 52 is virtually identical to the CLK_data signal inside the DAC 28. The DATACLK signal is used as a synchronization clock in the circuit 24. The DATACLK signal ensures that the DAC 28 and the circuit 24 are frequency synchronized. Synchronizing a phase between the digital data and the CLK_data signal of the DAC 28 becomes an issue when the DAC conversion speed increases, which leaves less time for the CLK_data signal to latch the incoming digital data.
DATACLK jitter, digital data jitter, data to clock setup time and hold time, data line to data line skew, temperature changes, semiconductor manufacturing process variations, and/or power supply variations also tend to reduce timing margin and tend to collapse a valid data window shown in FIG. 2 at relatively high data rates.
Referring now to FIG. 3, another data interface approach is shown. A system 60 includes a circuit 62 such as a FPGA, ASIC or other circuit. The circuit 62 may include a serializer circuit 68 that outputs digital data to a DAC 64 via a buffer 70. The DAC 64 includes a first in first out (FIFO) memory circuit 72 that receives the digital data, a CLK_fifo signal at a Clk_in input and a CLK_data signal at a Clk_out input. An output of the FIFO memory circuit 72 is output to a multiplexer 74. An output of the multiplexer 74 is transmitted to a DAC core 76.
The DAC 64 further includes a clock divider circuit 80 that receives a DAC clock (CLK_dac) signal. An output of the clock divider circuit 80 supplies the CLK_data signal to the multiplexer 74 and the FIFO circuit 72. A buffer 82 communicates with the clock divider circuit 80 and outputs a data clock (DATACLK) signal to a buffer 84 of the circuit 62. The buffer 84 transmits the DATACLK signal to the serializer circuit 68 and to a buffer 88, which generates and outputs the CLK_fifo signal to the FIFO memory circuit 72.
In this approach, the DATACLK signal generated by the DAC 64 is sent to the circuit 62 for data clocking and synchronization. A version of the DATACLK signal from the buffer 88 (the CLK_fifo signal) is transmitted back to the DAC 64 along with the digital data. The CLK_fifo signal latches the incoming digital data into the FIFO memory circuit 72. The digital data in the FIFO memory circuit 72 is clocked out by the CLK_data signal.
With enough FIFO depth, synchronization occurs between the two clock domains (CLK_fifo and CLK_data). While this approach can be implemented fully digitally and design synthesis tools may be used, the system 60 tends to consume relatively high power and generates digital noise and spurs in frequency spectrum that reduce DAC dynamic performance. In addition, this implementation requires large chip area, which increases cost.
Referring now to FIGS. 4 and 5, a system 100 includes a circuit 102 such as a FPGA, ASIC or other circuit. The circuit 102 may include a first serializer circuit 106 that outputs digital data to a DAC 104 via a buffer 108. The DAC 104 includes a multiplexer 112 that receives a clock data (CLK_data) signal and digital data. An output of the multiplexer 112 is transmitted to a DAC core 114. The DAC 104 further includes a clock divider circuit 116 that receives a DAC clock (CLK_dac) signal. An output of the clock divider circuit 116 supplies the CLK_data signal to the multiplexer 112 and a buffer 118.
The buffer 118 outputs a data clock (DATACLK) signal (via a conductor having a length L) to a buffer 120 of the circuit 102. The buffer 120 transmits the DATACLK signal to a first input of a digital clock management (DCM) circuit 122. An output of the DCM circuit 122 is output to first and second clock inputs of a second serializer circuit 124. An output of the second serializer circuit 124 is input to a delay circuit 126, which outputs a DCLK signal to a buffer 130. A second buffer 132 receives an output of the buffer 130. The second buffer 132 outputs the DCLK signal to a clock feedback input of the DCM circuit 122.
In use, the DATACLK signal generated by the DAC 104 is transmitted to the circuit 102 as a synchronization clock to clock out the digital data. The DATACLK signal is also used as a reference clock signal for DCM circuit 122 associated with the circuit 102. A conductor 150 that routes DCLK between the buffers 130 and 132 has a length (M+L). This length matches a sum of a length M of a conductor carrying the digital data from the buffer 108 to the multiplexer 112 and the length L of the conductor carrying the DATACLK signal from the buffer 118 to the buffer 120. For example, the conductor 150 can be a trace on a printed circuit board (PCB).
There is a fixed phase relationship between the CLK_data signal and the DATACLK signal as can be seen in FIG. 5, subject to PVT-induced delay changes of the output buffer. The length (L+M) of the conductor 150 can be made such that the DCLK signal is placed optimally for the required timing between the DCLK signal and the digital data for a given PVT case. Because the DCLK signal is locked by a delay locked loop inside the circuit 102, the DCLK signal has the same phase as the DATACLK signal with matched conductor lengths.
A phase relationship between the CLK_data signal and the digital data is fixed and optimized for a given PVT case. However, the optimal timing point may change with PVT changes due to the output buffer 118 inside the DAC 104, which may reduce the timing margin in the data interface.
In general, the DCM circuit 122 inside the circuit 102 has relatively large jitter. The output lines of the circuit 102 also tend to have relatively large skew. As a result, this approach tends to suffer reduced timing margin because of the jitter and skew. In addition, this approach may require manual tuning of the length M+L of the conductor 150 to obtain the proper timing.